CS 4420 - Computer Architecture

General Information

The nitty-gritty details about computer architectures. Focused primarily around processors, memories, and networks.

Prerequisites

ECE 2300, ECE 3140 / CS 3420 - Embedded Systems OR CS 3410 - Computer System Organization and Programming

Topics Covered

  • Processors
    • Microcoding
    • Pipelining
  • Memories
    • Cache architecture
    • Optimization
  • Networks
    • Topology
    • Routing
    • Flow Control
  • Advanced Topics
    • Superscalar execution
    • Branch prediction
    • Out-of-order execution
    • Register renaming and memory disambiguation
    • VLIW, vector, and multithreaded processors
    • Memory protection, translation, and virtualization
    • Memory synchronization, consistency, coherence

Workload

Fall 2011: Severe. Four long Verilog assignments (+ lab reports), two very long exams, four thick problem sets, and random quizzes pretty much every week.

Fall 2012: 4 Python assignments (+ lab reports) but there were supposed to be 5. Writing in Python was a lot simpler than Verilog. Two long and pretty difficult exams and four long problem sets. Random quizzes in lecture, but are pretty easy if you pay attention to the previous lecture. There were 17 in total.

Fall 2013: Severe. 5 long Verilog labs (+ lab reports), four very thick problem sets (to give you an idea, each handout was about 20 pages long), two 3 hour exams that should have been 4 hours long to be fair, and random quizzes pretty much every week. Expect to put in about 20 hours per lab.

Fall 2018: Workload has been reduced a little bit since 2013, although it is still quite substantial. At some point, lab 4 (the ring network) was removed, so there are only 4 lab assignments using either Python (PyMTL) or Verilog along with their corresponding lab reports. If subsequent offerings are anything like FA18, the first two problem sets will take forever (and multiple trips to OH), although the rest aren’t as bad. Exams are still both long and challenging. Expect a 10 minute quiz every single week.

General Advice

Comp arch is a ton of work for a CS major to do.

CS majors complain about OS assignments which are in Python, you don’t have to write test cases for, and have no report. They would hate comp arch being like legit.

Testimonials

I’m putting my advice here in testimonials, since my opinion is quite biased. I really enjoyed the material, thought Chris Batten’s teaching was great, but disagreed with pretty much everything else in the course. I would not recommend this course to any but the most interested, since the amount of busy work is astounding. Quizzes are unnecessary and stressful, since there’s rarely enough time to actually think about the problems. Labs took a lot of time, but I didn’t really learn much from them (probably my fault for being bad at debugging Verilog). Lab reports were a pain to write up, and I often got docked for not including random charts and data that it didn’t ask for. ’'’Extra credit is mandatory if you want an A’’’, which I think is a stupid and stressful requirement. Overall, grading felt arbitrary, which was really a stress I didn’t need during the semester I took this course.

I agree with pretty much everything said above. Pymtl, basically verilog in python, was pretty new so we didn’t have the “extra credit” for each assignment. The grading was a little arbitrary. Unless you put a ton of effort into your lab report you won’t be getting an A+. The labs are a lot easier to debug now since it’s now in python though the platform is still a little buggy. I think Batten’s teaching was amazing and the material taught was really interesting so I would definitely recommend this course.

Very interesting material, particularly the last half of the course. Batten is extremely organized and committed to the class, but the workload is unbearable. Everything about this class is stressful: do not take it unless you are confident you can dedicate a large majority of your work time to it every week. Lab reports count for most of your lab grade, even though doing the Verilog itself takes forever. It’s pretty much impossible to get an A in the class without doing extensions, so they are, in a way, required if you want the chance to do well. Their grading was also very delayed. We finished Lab 5 without knowing our grades for labs 2, 3, and 4. Exams, particularly this semester’s final, are absurdly long. It was nearly impossible to finish the final in 3 hours – it’s more of a test of your writing speed than your comprehension of the material. The class is also not curved, so an unfair exam will penalize everyone’s grade. I really wish this course was less stressful, because there’s a lot to learn from the material and Batten. I would not recommend this course unless it is your ’'’only’’‘ time sink.

FA18 update: Since the above testimonials, the course has definitely gotten itself together more. Extra credit is no longer required to get an A (in fact the median was an A-), and the course is likely curved a fair bit seeing as the averages for both exams were around 70. However, this class is still easily the hardest CS course I’ve taken so far (much, much harder than 3410 and 3110 in my opinion), with a ton of busywork as well. The class moves quickly as well, so don’t think for a moment that you can get away with zoning off in lecture for a little bit. That being said, this class is 100% worth it if you have any interest in lower level topics and computer architecture whatsoever. There is a ton of mind blowing material, and the instructors are fantastic at what they do as well. Definitely don’t take this class if you have a tough semester otherwise, but it isn’t nearly as bad as the other testimonials make it out to be anymore.

Past Offerings

Semester Time Professor Median Grade Course Page
Fall 2011 - Christopher Batten - -
Fall 2013 - Christopher Batten B+ http://www.csl.cornell.edu/courses/ece4750/
Fall 2018 - Christina Delimitrou A- http://www.csl.cornell.edu/courses/ece4750/

Resources

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